Current microprocessors and microcontrollers require input data at ever faster rates which exceed the limits of conventional memory technologies. Manufacturers of semiconductor memory devices are developing progressively faster memory architectures to allow the speed of the memories to be improved. One of these techniques is the burst mode of synchronous reading. This burst read mode allows the microprocessor to read data from the memory at a faster rate than in the customary random read mode.
At first, the microprocessor only supplies the memory address to the memory. The microprocessor then supplies a clock signal, and based upon a reading at a random access rate, the data is delivered from the memory at each rising edge of the clock signal. The frequency of the clock signal can be much higher than that of the random read signal. As a result, the data transfer rate can be increased significantly.
The next addresses are internally generated by the memory device. However, burst reading in Flash memories is limited by the number of successive words at the predetermined starting address. Since the memory usually can handle only four successive words, the term synchronous page mode applies.
Current semiconductor non-volatile memory devices can support the random read mode, which is asynchronous, as well as the burst read mode, which is synchronous. The standard read mode is, however, the random mode. Two different constructions are commonly used to enable burst reading.
A first approach uses a sequence of enable control signals. To operate in the burst read mode, the memory device is provided with three additional control pins. These control pins allow interface with a wide range of microprocessors. The control pins are generally designated as LBA (Load Burst Address), BAA (Burst Address Advance), and CLK Clock).
The burst read mode comprises an addressing step and a corresponding data step. During the addressing step, the pin LBA must be held low for one clock period. On the rising edge of the clock signal, the starting address of the burst mode is loaded into an internal counter of an address bus.
During the data step, the first available data of the burst mode is accessible after an access time tACC after the rising edge of the clock signal. For the next data, the signal on the pin BAA is activated, and the rising edge of the clock signal on the pin CLK will increase the count in the counter and supply the remaining data in the appropriate sequence within the specified access time tBACC. The data sequence is supplied for the duration of the signal at the pin BAA.
The accompanying FIG. 1 shows a graph of some signals plotted against the same time base for a memory device operated in the burst read mode previously described. This first approach has a major drawback in that, once the memory has entered the burst read mode, only this mode is permitted. To return to the random read mode, another control sequence needs to be provided or the configuration register needs to be re-initialized.
A second approach writes into a configuration register incorporated to the memory device. This approach is described in U.S. Pat. No. 5,903,496, for example. This second approach is even more elaborate than the previous one, since the bursting order, the clock signal frequency and the burst length are fixed. To change any of these values, the configuration register must be re-written.